1. Field of the Invention
The present invention relates to an effective technique for a method for manufacturing a thin film transistor (TFT) formed by laminating a semiconductor film and an insulating film over a substrate having an insulating surface. In addition, the present invention relates to an effective technique for a method for manufacturing a thin film transistor having a short-channel structure.
2. Description of the Related Art
In late years, a TFT has been formed by means of a semiconductor thin film (thickness of around several to several hundreds) formed over a substrate having an insulating surface, and development of a semiconductor device having a large area integrated circuit comprising this TFT has been advanced. An active matrix liquid crystal display device, an EL display device, and a contact type image sensor are known as the representative example. Besides, a system on panel provided with a CPU, a DRAM, an image processing circuit, a speech processing circuit in addition to a pixel portion and a drive circuit portion on the same substrate is proposed. In particular, because field-effect mobility is high in a TFT using a crystalline silicon film as an active region, a circuit comprising various functions (for example, a pixel circuit for displaying an image, drive circuits such as a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit for controlling the pixel circuits, a CPU, a SRAM, an image processing circuit, and a speech processing circuit, can be formed by using the TFT.
FIG. 10 shows a current-voltage characteristic (Id−Vd characteristic) of a TFT. In addition, a graph of the current-voltage characteristic of the TFT as shown in FIG. 10 shows a current magnitude Id flowing to a drain region of the TFT to Vd which is a voltage between a source region and a drain region. FIG. 10 is a plurality of graphs showing various value of Vg that is a voltage between a source region and a drain region of the TFT.
As shown in FIG. 10, the current-voltage characteristic of the TFT is divided into two regions by value of Vg and Vd. The region of |Vg−Vth|<|Vd| shows a saturation region, and the region of |Vg−Vth|>|Vd| shows a linear region.
The following formula 1 holds in a saturation region.
                              I          d                =                              W                          2              ⁢              L                                ⁢          μ          ⁢                                          ⁢                                                    C                ox                            ⁡                              (                                                      V                    g                                    -                                      V                    th                                                  )                                      2                                              [                  Formula          ⁢                                          ⁢          1                ]            
In addition, μ means mobility of the TFT, Cox means capacitance of a gate insulating film per a unit area, and W/L means a ratio of a channel-width W and a channel-length L in a channel forming region.
On the other hand, the following formula 2 holds in the linear region.
                              I          d                =                  μ          ⁢                                          ⁢                      C            ox                    ⁢                      W            L                    ⁢                      {                                                            (                                                            V                      g                                        -                                          V                      th                                                        )                                ⁢                                  V                  d                                            -                                                V                  d                  2                                2                                      }                                              [                  Formula          ⁢                                          ⁢          2                ]            
According to the formula 2, it can be thought that performance of the TFT in the linear region can be improved by means of the gate capacitance (Cox) and the ratio of the channel-width and the channel-length (W/L).
To make the capacitance (Cox) of the gate insulating film increased is conceivable as the first remedy. Specifically, there are techniques such as raising relative permittivity of the gate insulating film, making the film thickness thin, improving interfacial quality of a semiconductor layer and a gate insulating film, and the like (for example, Reference 1, Japanese Patent Laid-Open No. 2000-275678)
To make the ratio of the channel-width and the channel-length (W/L) further enlarged is conceivable as the second remedy. In other words, the channel width (W) of the TFT is to be magnified or the channel-length (L) is to be reduced.